TIM internal peripheral
目录
Article purpose
The purpose of this article is to
- briefly introduce the TIM peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- explain how to configure the TIM peripheral
Peripheral overview
The TIM peripheral is a multi-channel timer unit, available in various configurations, depending on the instance used. There are basically following categories: advanced-control timers, general-purpose timers and basic timers.
The TIM can provide: PWM with complementary output and dead-time insertion, break detection, input capture[1], quadrature encoder[2] interface (typically used for rotary encoders), trigger source for other internal peripherals like: ADC[3], DAC[4], DFSDM[5].
Features
The TIM peripheral is available in different configurations, depending on the selected instance :
- TIM1 and TIM8 are advanced-control timers, with 6 independent channels.
- TIM2, TIM3, TIM4 and TIM5 are general-purpose timers, with 4 independent channels.
- TIM12, TIM13 and TIM14 are general-purpose timers, with 2 (TIM12) or 1 (TIM13 and TIM14) independent channels.
- TIM15, TIM16 and TIM17 are also general-purpose timers, with 2 (TIM15) or 1 (TIM16 and TIM17) independent channels. Compare to TIM12, TIM13 and TIM14, this configuration brings some features that are very useful for motor control (like break function, DMA burst mode control, complementary output with dead-time insertion, ...)
- TIM6 and TIM7 are basic timers
Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
Security support
The TIM is a non-secure peripheral.
Peripheral usage and associated software
Boot time
The TIM is not used at boot time.
Runtime
Overview
TIM12 and/or TIM15 can be allocated to:
- the Arm® Cortex®-A7 secure core to be controlled in the secure monitor (TF-A or OP-TEE), to perform HSI and CSI calibrations[6] in RCC.
All TIM instances can be allocated to:
or
- the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by TIM HAL driver
Note that RCC[7] owns one prescaler per TIM group corresponding to APB1 and APB2 buses: TIMG1PRE and TIMG2PRE, respectively. The allocation to Cortex-A7 or the Cortex-M4 should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below (#Peripheral assignment).
Software frameworks
| Domain | Peripheral | Software frameworks | Comment | ||
|---|---|---|---|---|---|
|
Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) |
|||
| Core/Timers | TIM |
TF-A TIM driver OP-TEE TIM driver |
Linux PWM framework Linux IIO framework |
STM32Cube TIM driver | |
Peripheral configuration
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.
For Linux kernel configuration, please refer to TIM device tree configuration and TIM Linux driver articles.
Peripheral assignment
Internal peripherals assignment table template
| rowspan="14" | Core/Timers | rowspan="14" | TIM | TIM1 (APB2 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM2 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM3 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM4 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM5 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM6 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM7 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM8 (APB2 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM12 (APB1 group) | ☐ | ☐ | ☐ | Assignment (single choice) |- | TIM13 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM14 (APB1 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM15 (APB2 group) | ☐ | ☐ | ☐ | Assignment (single choice) |- | TIM16 (APB2 group) | | ☐ | ☐ | Assignment (single choice) |- | TIM17 (APB2 group) | | ☐ | ☐ | Assignment (single choice) |-
|}
How to go further
STM32 cross-series timer overview[8] application note.
