“QUADSPI device tree configuration”的版本间的差异

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2020年11月10日 (二) 11:48的最新版本

Article purpose

本文介绍如何在将 QUADSPI internal peripheral 分配给 Linux®操作系统时对其进行配置。 在这种情况下,它由MTD framework控制.

使用device tree 机制执行配置,该机制提供由STM32 QUADSPI Linux驱动程序和MTD框架使用的QUADSPI外围设备的硬件描述。


如果外围设备已分配给另一个执行上下文,请参阅[[[How to assign an internal peripheral to a runtime context]] 文章,了解有关外围设备分配和配置的指南。

DT bindings documentation

QUADSPI设备树绑定由以下组成:

  • generic SPI-NOR / SPI-NAND Flash memory bindings [1].
  • QUADSPI driver bindings [2].

在接下来的章节中,SPI-NAND绑定只与ecosystem release ≥ v1.1.0{{#set:Ecosystem release=revision of a previous flow 1.1.0}} 兼容。

DT configuration

该硬件描述是“STM32微处理器”设备树文件(扩展名为.dtsi)和“板子”设备树文件(扩展名为.dts)的组合。 有关设备树文件分割的说明,请参见Device tree. STM32CubeMX可用于生成板设备树。 有关详细信息,请参阅How to configure the DT using STM32CubeMX

DT configuration (STM32 level)

QUADSPI外设节点位于``stm32mp157c.dtsi[3] 文件。

   qspi: spi@58003000 {                                      Comments
       compatible = "st,stm32f469-qspi";
       reg = <0x58003000 0x1000>,                            --> Register location
             <0x70000000 0x10000000>;                        --> Memory mapping address
       reg-names = "qspi", "qspi_mm";
       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;        --> The interrupt number used
       dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,         --> DMA specifiers [4]
              <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
       dma-names = "tx", "rx";
       clocks = <&rcc QSPI_K>;
       resets = <&rcc QSPI_R>;   
       status = "disabled";
   };

Warning.png 与STM32相关的该设备树部分应保持原样,客户不应对其进行修改。

DT configuration (board level)

QUADSPI外设最多可连接2个SPI-NOR闪存。

SPI-NOR闪存节点[1] 必须是QUADSPI外设节点的子级。

   &qspi {                                                   Comments
       pinctrl-names = "default", "sleep";                   --> For pinctrl configuration, please refer to Pinctrl device tree configuration
       pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
       pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                         --> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";                                      --> Enable the node
flash0: mx66l51235l@0 { compatible = "jdec,spi-nor"; reg = <0>; --> Chip select number spi-rx-bus-width = <4>; --> The bus width (number of data wires used) spi-max-frequency = <108000000>; --> Maximum SPI clocking speed of device in Hz #address-cells = <1>; #size-cells = <1>; }; };

DT configuration example

以下示例显示了在连接1个SPI-NAND闪存和1个SPI-NOR闪存时如何配置QUADSPI外设。

   &qspi {                                                    
       pinctrl-names = "default", "sleep";                    
       pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
       pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                          
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";
flash0: mx66l51235l@0 { compatible = "jdec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; };
flash1: mt29f2g01abagd@1 { compatible = "spi-nand"; reg = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <133000000>; #address-cells = <1>; #size-cells = <1>; }; };

How to configure the DT using STM32CubeMX

STM32CubeMX 工具可用于配置STM32MPU设备并获取相应的platform configuration device tree文件。
STM32CubeMX可能不支持上述DT bindings documentation p段落中描述的所有属性。 如果是这样的话,该工具会在生成的设备树中插入“”User Sections“”。 然后可以编辑这些部分以添加某些属性,并将它们代代相传。 有关详细信息,请参阅STM32CubeMX 用户手册。