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PWR internal peripheral
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==Article purpose== The purpose of this article is to: * briefly introduce the PWR peripheral and its main features * indicate the level of security supported by this hardware block * explain how it can be allocated to the three runtime contexts and linked to the corresponding software components * explain, when necessary, how to configure the PWR peripheral. ==Peripheral overview== The '''PWR''' peripheral is used to control the device power supply configuration.<br /> It has 6 input pins (named wakeup pins) which can be programmed to wake the system up from low power. The wakeup pins are listed with '''WKUP''' prefix in the [[STM32MP15 resources#DS12505|STM32MP15 Datasheet]]. These pins can be used by the Cortex<sup>®</sup>-A7 non secure (via Cortex<sup>®</sup>-A7 secure services) or the Cortex<sup>®</sup>-M4. The PWR peripheral provides 2 output hardware lines named PWR_ON and PWR_LP: * In [[PMIC hardware components#STPMIC1|STPMIC1]] configuration, PWR_ON allows to select the register bank (active or low power). PWR_LP is not used. * In the power discrete solution they drive VDDcore which feeds the Cortex<sup>®</sup>-A7, the Cortex<sup>®</sup>-M4 and the peripherals. They also control the DDR power supplies (VDD_DDR, VREF_DDR, VTT_DDR). ===Features=== Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented. ===Security support=== The PWR is '''secure aware''' with the security control managed via [[RCC internal peripheral|RCC]] '''TZEN''' bit. ==Peripheral usage and associated software== ===Boot time=== The PWR is closely configured together with [[RCC internal peripheral|RCC]] by all the [[Boot chain overview|boot components]]: the ROM code, the FSBL, the SSBL and up to Linux<sup>®</sup> kernel. Its configuration is carried by the [[Device tree|device tree]]. ===Runtime=== ====Overview==== The PWR peripheral is shared at runtime: * the Cortex<sup>®</sup>-A7 secure controls all secure registers (cf. TZEN description above) with [[OP-TEE overview|PWR OP-TEE driver]]. and * the Cortex<sup>®</sup>-A7 non-secure mainly controls it via the [[Regulator overview|regulator framework]] and the [[Interrupt overview|interrupt framework]] in Linux and * the Cortex<sup>®</sup>-M4 controls it in STM32Cube with [[STM32CubeMP1 architecture|PWR HAL driver]] <br /> A concurrent control from each context is possible because the described management is realized via independent registers. ====Software frameworks==== {{:Internal_peripherals_software_table_template}} | Power & Thermal | [[PWR internal peripheral|PWR]] | [[OP-TEE_overview|OP-TEE PWR driver]] | [[Regulator overview|Linux regulator framework]] | [[STM32CubeMP1 architecture|STM32Cube PWR driver]] | |- |} ====Peripheral configuration==== The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article. ====Peripheral assignment==== {{:Internal_peripherals_assignment_table_template}} <onlyinclude> | rowspan="1" | Power & Thermal | rowspan="1" | [[PWR internal peripheral|PWR]] | PWR | <span title="system peripheral" style="font-size:21px">✓</span> | <span title="system peripheral" style="font-size:21px">✓</span> | <span title="system peripheral" style="font-size:21px">✓</span> | |- </onlyinclude> |} ==How to go further== The PWR is interfaced with the hardware debug port ([[HDP internal peripheral|HDP]]) of the STM32MP15. This link offers the flexibility to observe the main PWR state signals on debug pins. Please refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the exact list of signals that can be monitored. ==References== <references/> <noinclude> [[Category:Power and Thermal peripherals]] {{ArticleBasedOnModel | Internal peripheral article model}} {{PublicationRequestId | 9334 | 2018-10-31| AlainF}} </noinclude>
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